As semiconductor devices are scaled down, dimensional and overlay precisions for required patterns become stricter and requirements for those measurement precisions become stricter, accordingly. According to the International Technology Roadmap for Semiconductors (ITRS), for example, the overlay precision of 8 to 10 nm is required for logic 22 nm nodes (interconnect lines HP 40 nm), and the overlay precision of 6 to 8 nm is required for logic 15 nm nodes (interconnect lines HP 32 nm). Furthermore, the double patterning process is applied to nodes after the logic 22 nm nodes. In this case, the overlay precision has an influence on the dimensional precision; therefore, the overlay precision between double patterning patterns becomes quite strict to be equal to or smaller than 5 nm. To meet this overlay requirement, a high-precision overlay measurement technique is necessary. If Precision/Tolerance (P/T) is assumed as 0.2, the necessary measurement precision is 5 nm×0.2=1.0 nm. Note that this measurement precision represents not only a repeatable/reproducible precision but also comprehensive measurement uncertainty including the absolute value precision and reproducible precision of measurement values.
As the overlay measurement technique, the optical measurement technique has been conventionally, widely used. In the optical measurement, an overlay measurement-dedicated pattern at a size of approximately 20 to 40 μm is necessary and the pattern has been normally inserted into a dicing region in a corner of a chip because of the size. As a result, the overlay measurement-dedicated pattern is apart from an on-chip actual device region, and there occurs approximately a few nm of an overlay measurement value error resulting from the difference in on-chip position and the difference between a position measurement-dedicated pattern and an actual pattern. Since this error is not allowed for the nodes after the 22 nm nodes, it is necessary to measure the overlay near the on-chip device. Furthermore, as regards on-chip overlay distribution correction, only linear components have been conventionally corrected using chip four-corner data. However, as the precision improves, it becomes indispensable to correcting higher-order components, and multipoint measurement including the on-chip overlay measurement becomes necessary on a product mask.
Recently, a measurement scheme with a measurement pattern made small in size has been developed so that the measurement pattern can be disposed near an actual device in the optical measurement technique. This scheme has, however, the following problems. The edge length of the measurement pattern is reduced, and the random variation reduction effect derived from the signal averaging effect is reduced as a result of the shorter edges, so that the measurement precision degrades. In this case, if the size of the measurement pattern is equal to or smaller than 10 μm, the measurement precision required for the nodes after the 22 nm nodes cannot be achieved. On the other hand, if the size of the measurement pattern is equal to or larger than 10 μm, the placement of the measurement pattern near the actual device is limited.
To solve the abovementioned problems, the overlay measurement technique using electron beams has been developed as an alternative for the optical measurement technique. As a typical example of the overlay measurement technique, there is known a technique using a scanning electron microscope (CD-SEM). With the overlay measurement technique using electron beams, a measurement pattern can be made small in size or an actual device itself can be measured. It is, therefore, possible to measure the overlay in the actual device region.
With the overlay measurement using the abovementioned scanning electron microscope, if a first pattern and a second pattern for measuring overlay misalignment are both present on a substrate surface, relative positions of the two patterns can be measured using secondary electron signals by a shape contrast similarly to the normal critical dimension. On the other hand, if the second pattern is not present on the substrate surface but buried in a lower layer, for example, a substrate is electrically charged by irradiating the substrate with electron beams at a higher acceleration and higher current than the normal critical dimension and a voltage contrast resulting from a difference in the structure of the lower layer is detected. It is thereby possible to detect the position of the lower layer pattern, as disclosed in Patent Literatures 1 and 2. However, as disclosed in Patent Literature 1, if the electron beams are scanned in the same direction as a direction of the overlay misalignment measurement, a signal waveform becomes asymmetrical due to the asymmetry of an amount of electric charge along an electron beam scan direction, resulting in the occurrence of an offset in an overlay misalignment measurement result. FIG. 1(a) shows this example.
Next, as disclosed in Patent Literature 2, if electron beams are scanned in a direction perpendicular to the direction of overlay misalignment measurement, the asymmetry of the amount of electric charge along the electron beam scan direction does not cause an offset in the direction of overlay misalignment measurement. It is, therefore, possible to reduce the measurement offset. FIG. 1(b) shows this example. Moreover, FIGS. 2(a) and 2(b) show situations where asymmetrical electric charge occurs in the lower layer pattern section in the electron beam scanning in FIGS. 1(a) and 1(b), respectively. When the inventors measured the overlay misalignment by inverting the scan direction and the scan sequence in order to evaluate the measurement offset in the measurement as shown in FIG. 1(b), a measurement value error of approximately 1 nm was generated. This is because the asymmetry of the amount of electric charge occurs due to the scan sequence and an offset occurs in the direction of overlay misalignment measurement as shown in FIG. 2(b). Furthermore, Patent Literature 2 discloses, as a conventional technique, a scheme for changing a scan method between a central portion of the scan region and a peripheral portion thereof in order to make uniform amounts of electric charge within an electron beam scan region and to suppress a potential gradient. In addition, Patent Literature 2 discloses, as a conventional technique, a method and an apparatus for changing a scan viewpoint in the direction perpendicular to each scan line by a predetermined amount in a predetermined direction in order to suppress the amount of electric charge inherent in the scan method and generated by scanning of an electron beam across one frame. However, the techniques of Patent Literature 2 have the same problems that the signal waveform becomes asymmetrical due to the asymmetry of the amount of electric charge based on the electron beam scanning.